Variation-aware high-level DSP circuit design optimisation framework for FPGAs

The constant technology shrinking and the increasing demand for systems that operate under different power profiles with the maximum performance, have motivated the work in this thesis. Modern design tools that target FPGA devices take a conservative approach in the estimation of the maximum performance that can be achieved by a design when it is placed on a device, accounting for any variability in the fabrication process of the device. The work presented here takes a new view on the performance improvement of DSP designs by pushing them into the error-prone regime, as defined by the synthesis tools, and by investigating methodologies that reduce the impact of timing errors at the output of the system. In this work two novel error reduction techniques are proposed to address this problem. One is based on reduced-precision redundancy and the other on an error optimisation framework that uses information from a prior characterisation of the device. The first one is a generic architecture that is appended to existing arithmetic operators. The second defines the high-level parameters of the algorithm without using extra resources. Both of these methods allow to achieve graceful degradation whilst variation increases. A comparison of the new methods is laid against the existing methodologies, and conclusions drawn on the tradeoffs between their cost, in terms of resources and errors, and their benefits in terms of throughput. In some cases it is possible to double the performance of the design while still producing valid results.Open Acces

Stochastic Theater: Stochastic Datapath Generation Framework for Fault-Tolerant IoT Sensors

Stochastic Computing has emerged as a competitive computing paradigm that produces fast and simple implementations of arithmetic operations, while offering high levels of parallelism, and graceful degradation of the results when in the presence of errors. IoT devices are often operate under limited power and area constraints and subjected to harsh environments, for which, traditional computing paradigms struggle to provide high availability and fault-tolerance. Stochastic Computing is based on the computation of pseudo-random sequences of bits, hence requiring only a single bit per signal, rather than a data-bus. Notwithstanding, we haven’t witnessed its inclusion in custom computing systems. In this direction, this work presents Stochastic Theater, a framework to specify, simulate, and test Stochastic Datapaths to perform computations using stochastic bitstreams targeting IoT systems. In virtue of the granularity of the bitstreams, the bit-level specification of circuits, high-performance characteristics and reconfigurable capabilities, FPGAs were adopted to implement and test such systems. The proposed framework creates Stochastic Machines from a set of user defined arithmetic expressions, and then tests them with the corresponding input values and specific fault injection patterns. Besides the support to create autonomous Stochastic Computing systems, the presented framework also provides generation of stochastic units, being able to produce estimates on performance, resources and power. A demonstration is presented targeting KLT, typical method for data compression in IoT applications

XtokaxtikoX: a stochastic computing-based autonomous cyber-physical system

This paper presents XtokaxtikoX, a fully autonomous cyber-physical system employing only stochastic arithmetic to perform computations on its data-path. Traditional implementations of stochastic computing systems benefit from fast and compact implementation of arithmetic operators, and high tolerance to errors, but depend heavily on the conversion between stochastic bitstreams and binary to implement many parts of the system. Furthermore, if a system requires any interaction with analog electronic components it must have additional ADC/DAC conversion circuitry, which further increases the complexity of the system. Conversely, the proposed work is able to directly translate analog signals into stochastic bitstreams, process the stochastic bitstreams and finally control analog actuators relying only on the information on the stochastic bitstreams. Details on the architectures to accomplish such functionality are presented as well as other stochastic arithmetic units. This paper also presents a small stochastic computing-based autonomous cyber-physical system implemented on a Cyclone IV FPGA to carry out a proof-of-concept.info:eu-repo/semantics/publishedVersio

On the Feasibility of GPON Fiber Light Energy Harvesting for the Internet of Things

The emerging concept of smart cities demands for a large number of electronic devices, like sensors and actuators, distributed over several public spaces and buildings. The Internet of Things (IoT) has a key role in connecting devices to the Internet. However, the significant number of devices makes the maintenance task of the entire network difficult and expensive. To mitigate this problem, considerable research efforts have been made to develop energy-aware devices capable of self-sustainable operation, by harvesting their energy from various sources. In this paper, we study the possibility of harvesting energy from the light flowing in the Gigabit Passive Optics Network (GPON) to supply low-power devices. Since most cities already have a working GPON installation, using this installation to interconnect and power IoT devices can be a viable and less expensive solution, instead of installing new dedicated networks. This is also an interesting solution to convey communications and energy to low-power applications where access to the power grid is unfeasible. This study is focused in the 1550 nm wavelength, whose available optical power, in residential premises, is between -7 dBm and +2 dBm. With this range of optical power, and with a 30% efficiency photodiode, we show, for the worst-case scenario of the GPON, how it is possible to harvest 62 µW of energy at the Maximum Power Point (MPP)

Energy-efficient and real-time wearable for wellbeing-monitoring IoT system based on SoC-FPGA

Wearable devices used for personal monitoring applications have been improved over the last decades. However, these devices are limited in terms of size, processing capability and power consumption. This paper proposes an efficient hardware/software embedded system for monitoring bio-signals in real time, including a heart rate calculator using PPG and an emotion classifier from EEG. The system is suitable for outpatient clinic applications requiring data transfers to external medical staff. The proposed solution contributes with an effective alternative to the traditional approach of processing bio-signals offline by proposing a SoC-FPGA based system that is able to fully process the signals locally at the node. Two sub-systems were developed targeting a Zynq 7010 device and integrating custom hardware IP cores that accelerate the processing of the most complex tasks. The PPG sub-system implements an autocorrelation peak detection algorithm to calculate heart rate values. The EEG sub-system consists of a KNN emotion classifier of preprocessed EEG features. This work overcomes the processing limitations of microcontrollers and general-purpose units, presenting a scalable and autonomous wearable solution with high processing capability and real-time response.info:eu-repo/semantics/publishedVersio

Onboard processing of synthetic aperture radar backprojection algorithm in FPGA

Synthetic aperture radar is a microwave technique to extracting image information of the target. Electromagnetic waves that are reflected from the target are acquired by the aircraft or satellite receivers and sent to a ground station to be processed by applying computational demanding algorithms. Radar data streams are acquired by an aircraft or satellite and sent to a ground station to be processed in order to extract images from the data since these processing algorithms are computationally demanding. However, novel applications require real-time processing for real-time analysis and decisions and so onboard processing is necessary. Running computationally demanding algorithms on onboard embedded systems with limited energy and computational capacity is a challenge. This article proposes a configurable hardware core for the execution of the backprojection algorithm with high performance and energy efficiency. The original backprojection algorithm is restructured to expose computational parallelism and then optimized by replacing floating-point with fixed-point arithmetic. The backprojection core was integrated into a system-onchip architecture and implemented in a field-programmable gate array. The proposed solution runs the optimized backprojection algorithm over images of sizes 512 x 512 and 1024 x 1024 in 0.14 s (0.41 J) and 1.11 s (3.24 J), respectively. The architecture is 2.6x faster and consumes 13x less energy than an embedded Jetson TX2 GPU. The solution is scalable and, therefore, a tradeoff exists between performance and utilization of resources.info:eu-repo/semantics/publishedVersio

Moving deep learning to the edge

Este trabalho foi financiado pelo Concurso Anual para Projetos de Investigação, Desenvolvimento, Inovação e Criação Artística (IDI&CA) 2019 do Instituto Politécnico de Lisboa. Código de referência IPL/2019/inCNeuraINet_ISELDeep learning is now present in a wide range of services and applications, replacing and complementing other machine learning algorithms. Performing training and inference of deep neural networks using the cloud computing model is not viable for applications where low latency is required. Furthermore, the rapid proliferation of the Internet of Things will generate a large volume of data to be processed, which will soon overload the capacity of cloud servers. One solution is to process the data at the edge devices themselves, in order to alleviate cloud server workloads and improve latency. However, edge devices are less powerful than cloud servers, and many are subject to energy constraints. Hence, new resource and energy-oriented deep learning models are required, as well as new computing platforms. This paper reviews the main research directions for edge computing deep learning algorithms.info:eu-repo/semantics/publishedVersio

Hybrid dot-product calculation for convolutional neural networks in FPGA

Este trabalho foi financiado pelo Concurso Anual para Projetos de Investigação, Desenvolvimento, Inovação e Criação Artística (IDI&CA) 2018 do Instituto Politécnico de Lisboa. Código de referência IPL/2018/LiteCNN_ISELConvolutional Neural Networks (CNN) are quite useful in edge devices for security, surveillance, and many others. Running CNNs in embedded devices is a design challenge since these models require high computing power and large memory storage. Data quantization is an optimization technique applied to CNN to reduce the computing and memory requirements. The method reduces the number of bits used to represent weights and activations, which consequently reduces the size of operands and of the memory. The method is more effective if hybrid quantization is considered in which data in different layers may have different bit widths. This article proposes a new hardware module to calculate dot-products of CNNs with hybrid quantization. The module improves the implementation of CNNs in low density FPGAs, where the same module runs dot-products of different layers with different data quantizations. We show implementation results in ZYNQ7020 and compare with state-of-the-art works. Improvements in area and performance are achieved with the new proposed module.info:eu-repo/semantics/publishedVersio